IP Logic Design Engineer
Altera· Bengaluru, Karnataka, India
seen live 22h ago
Job Details: Job Description: About the role Altera is looking for a hands-on Senior RTL Design Engineer to lead FPGA design and platform enablement for Altera development kits. This role spans architecture, Verilog/SystemVerilog implementation, Quartus flows and timing closure,
This link goes straight to the employer's workday page. Posted 14 days ago.We last confirmed it was open 22h ago.